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Chapter 2: Getting Started
Qsys Design Flow
Figure 2–2 shows a block diagram of an example Qsys system.
Figure 2–2. Qsys System
RapidIO
Simulation
Testbench Module
RapidIO
MegaCore Function
System Interconnect
2–5
DMA
On-Chip
FIFO
Qsys System
On-Chip
Memory
f
For Information About
System interconnect
Qsys
Quartus II software
Refer To
Qsys Interconnect and System Design Components chapter
in volume 1 of the Quartus II Handbook and the Avalon
Interface Specifications
System Design with Qsys section in volume 1 of the
Quartus II Handbook
Quartus II Help
For information about converting an SOPC Builder system that includes a RapidIO IP
core to a Qsys system, refer to Appendix C, Porting a RapidIO Design from the
Previous Version of the Software .
Specifying Parameters
To specify RapidIO parameters using the Qsys flow, follow these steps:
1. Create a new Quartus II project using the New Project Wizard available from the
File menu.
2. On the Tools menu, click Qsys .
3. On the System Contents tab, double-click RapidIO , or select RapidIO and click
Add, to add the RapidIO IP core to your system. The RapidIO parameter editor
appears.
May 2013
Altera Corporation
RapidIO MegaCore Function
User Guide
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